Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-bit SAR ADC Hua Fan1, Franco Maloberti2, Dagang Li 3, Daqian Hu, Yuanjun Cen3 and Hadi Heidari4 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, School of Microelectronics and Solid-State Electronics, ...
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In this paper, a novel capacitor self-calibration technique is presented, which can be used in high resolution ADCs, such as SAR ADC and pipeline ADC. The capacitors achieve self-calibration through the adjusting capacitors array and successive approximation (SAR) logic. A 14-bit SAR ADC using capacitor self-calibration technique we proposed has been designed. The …
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This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset …
Table 1. Resistance to capacitance range mapping Using reference capacitors to verify the 8588A The value of a typical reference capacitor commonly found in calibration laboratories changes with frequency and its configuration as a 2-terminal or 3-terminal device.
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calibration of the co mmercial bridge. The calibratio n results JUNG et al.: FABRICA TION OF CAPACITOR–RESIST OR BANK FOR CALIBRATING COMMERCIAL CAP ...
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A novel digital calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. The capacitor mismatches are extracted based on the comparator metastability and intrinsic noise. The proposed technique does not require additional external control sequences or any modification of the main DAC. The simulation results of a 12-bit SAR ADC with 10% capacitor …
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A foreground digital self-calibration technique that improves capacitor matching of a digital-to-analogue converter (DAC) employed in successive approximation register (SAR) analogue-to-digital conve... On the right-hand side of (), the average value of V IN (n) − V IN (n + 1) is almost negligible because the ramp speed is set to be slow so that the input sample-to …
match in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time-to-Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ...
To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time-to-Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to
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calibration is of the direct null type, and the capac- itor calibration is of the comparative null type. In other words, the accuracy of the capacitance mea- surements ultimately depends on the uncertainty in assigning a value to a standard capacitor. The stan
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To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time-to-Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ADCs.
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