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Fig. 3 Proposed capacitor mismatches calibration before calibration after calibration ENOB, bits 4 bit improvement mismatch error, % 10–2 14 13 12 11 10 9 10–3 Fig. 4 Monte Carlo simulation with added capacitor mismatches in split-CDAC Capacitor mismatch calibration: Fig. 3 presents the proposed capacitor mismatch calibration logics.
In this paper, a novel capacitor self-calibration technique is presented, which can be used in high resolution ADCs, such as SAR ADC and pipeline ADC. The capacitors achieve self-calibration through the adjusting capacitors array and successive approximation (SAR) logic. A 14-bit SAR ADC using capacitor self-calibration technique we proposed has been designed. The …
between the calibration of voltage transformers and capacitors at NIST. The voltage transformer calibration is of the direct null type, and the capac- itor calibration is of the comparative null type. In other words, the accuracy of the capacitance mea- surements ultimately depends on the uncertainty in assigning a value to a standard capacitor.
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2. Capacitance Calibration The precision measurement of capacitors for the purpose of calibration is generally based on a national primary standard of high accuracy, secondary/working Standards derived from it, and a capacitance- (or LCR-) meter used for the measurement (i.e. calibration) of the devices under test (DUT). This meter is normally
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This paper proposes a new capacitor recombination calibration method to compensate the capacitor mismatch of successive approximation register analog-to-digital converter (SAR ADC). This method focuses on automatically calibrating the mismatch of the SAR ADC capacitors to improve the static performance (Integral Non-Linearity, INL; Differential NonLinearity, DNL) …
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2. Capacitance Calibration The precision measurement of capacitors for the purpose of calibration is generally based on a national primary standard of high accuracy, secondary/working …
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A foreground digital self-calibration technique has been described. The calibration technique improves capacitor matching without using additional circuits and extensive computation. Applied to a 12 bit SAR ADC with 10% capacitor mismatch, SNDR is increased from 44.12 to 72.85 dB, resulting in 4.77 bit improvement of ENOB.
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A novel capacitor mismatch calibration method is presented to compensate the capacitor mismatches in a successive approximation register (SAR) ADC. The method features a new weight-balancing split capacitive DAC which allows automatic extraction and calibration of the capacitor mismatches by itself. As a result, the ADC''s resolution can be ...
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A novel capacitor mismatch calibration method is presented to compensate the capacitor mismatches in a successive approximation register (SAR) ADC. The method features a new weight-balancing split capacitive …
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